Integrated circuits are fabricated on a wafer to form a semiconductor die, which is then mounted within a package. The die includes a pattern of semiconductor devices, such as transistors, resistors and diodes, which are fabricated on the wafer. The devices are electrically interconnected with one another through one or more segments of conductive material, which extend along predetermined routing layers. The conductive segments on one routing layer are electrically coupled to conductive segments or devices on other layers through conductive vias. Electrical power is distributed throughout die by a plurality of power supply busses or rails, which are also formed of conductive segments that are routed along the various routing layers.
The package has a plurality of input and output pins for communicating with the semiconductor devices on the die. In addition, the package has one or more power supply pins for supplying power to the power supply rails on the die. During operation, large numbers of transistors on the die switch states on the clock edges. When a transistor changes its output state, the transistor either sinks current from the power supply rails to charge the interconnect capacitance at its output or sources current to the power supply rails to discharge its output capacitance. In essence, the interconnect capacitance at the outputs of the transistors share charge with the external power supply that is coupled to power supply pins of the package.
Due to the large distances between the power supply pins and the individual transistors on the die, the charge sharing between the external power supply and the transistor outputs on the die is relatively insufficient and can generate noise on the transistor outputs and on the voltage levels at the supply rails. A typical method of suppressing this noise and providing a more stable supply voltage is to couple a large internal or external capacitance between the power supply rails. Initially, large capacitors were coupled across the power supply pins of the package. More recently, the capacitance has been moved onto the die by coupling large arrays of parallel transistors between the power supply rails. For example, large arrays of P-channel metal oxide semiconductor (MOS) transistors can be coupled together in parallel with their gates coupled to the positive supply rail and their drains and sources coupled to the negative (ground) supply rail.
However, the amount of capacitance needed to decouple or stabilize the power rails on integrated circuits increases with each new technology generation. As semiconductor devices continue to become smaller, the channel lengths of the transistors decrease, which decreases the maximum voltage that can be applied across the channel. Therefore, the voltage levels that are used to bias the transistors have also decreased. The decrease in channel length in combination with the need to maintain small voltage tolerances makes stabilization of the power supply rails even more critical.
There are several approaches that are being used to address these problems. First, more capacitance is being added between the supply rails on the die per logic function. However this is becoming difficult to achieve with higher circuit densities since unused areas in which the decoupling capacitors can be fabricated are becoming smaller. The capacitance per unit gate or function cannot be increased without blocking usable die area. Second, more logic functions are being performed in an asynchronous manner to reduce the clock-induced change in supply voltage over time. Third, clock skew has been introduced to reduce the number of simultaneously switching events in the logic. While these methods have helped stabilize the power supply voltages, they each have an associated cost and may not be sufficient for future technologies.
Improved on-die power supply structures are desired for further reducing power bus transients.